The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2026
Filed:
Aug. 10, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Yu-Yi Huang, Taipei City, TW;
Yu-Hao Kuo, Hsinchu County, TW;
Chiao-Chun Chang, Hsinchu County, TW;
Jui-Hsuan Tsai, Taipei City, TW;
Yu-Hung Lin, Taichung City, TW;
Shih-Peng Tai, Xinpu Township, Hsinchu County, TW;
Jih-Churng Twu, Hsinchu County, TW;
Chen-Hua Yu, Hsinchu City, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of forming a semiconductor package is provided. The method includes forming a micro lens recessed from the top surface of a substrate. A concave area is formed between the surface of the micro lens and the top surface of the substrate. The method includes depositing a first dielectric material that fills a portion of the concave area using a spin coating process. The method includes depositing a second dielectric material that fills the remainder of the concave area and covers the top surface of the substrate using a chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.