The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Mar. 01, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chou-Kun Lin, Hsinchu, TW;

Harsha Vardhan Penugonda, Hsinchu, TW;

Monsen Liu, Hsinchu, TW;

King-Ho Tam, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 70/05 (2026.01); H10W 70/093 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/701 (2026.01);
Abstract

An interconnection structure (for a multi-chip interposer) includes: a first via stack at a first one amongst locations, the locations correspondingly being defined relative to first and second perpendicular directions, the via stack including vias stacked over each other in a third direction perpendicular to each of the first and second directions; a transition segment in a transition layer and overlapping and coupled to an uppermost one of the vias in the via stack at the first location, the transition segment being conductive and extending in at least the first direction or the second direction to overlap a second one of locations offset from the first location; and a first contact bump at the second location and over and coupled to the via stack.


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