The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jul. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chieh-En Chen, Tainan, TW;

Chen-Hsien Lin, Tainan, TW;

Shyh-Fann Ting, Tainan, TW;

Hsing-Chih Lin, Tainan, TW;

Dun-Nian Yaung, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/562 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2224/32146 (2013.01); H01L 2224/32235 (2013.01); H01L 2224/48157 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/13091 (2013.01);
Abstract

An integrated chip including a semiconductor substrate having a first side and a second side, opposite the first side. A first transistor and a second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. A first metal line is within the dielectric structure. A second metal line is within the dielectric structure and under the first metal line. A first metal via extends between the first metal line and the second metal line. A through-substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, to the first metal line and the second metal line.


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