The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2026
Filed:
Oct. 31, 2022
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/31 (2020.01); G06F 30/33 (2020.01);
U.S. Cl.
CPC ...
G06F 30/31 (2020.01); G06F 30/33 (2020.01);
Abstract
Disclosed is an improved approach to implement concurrent processing of 3D-IC electronic designs using a die interface model. Instead of a die-by-die approach that implements each die separately, the concurrent multi-die approach permits the multiple dies to be physically implemented simultaneously, without prior budgeting and margins.
Deng, Liqun. (2026). Method of die interface modeling for concurrent multi-die implementation of three-dimensional integrated circuit (3d-ic) (U.S. Patent No. 12632626). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12632626
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile