The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jan. 06, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsing-Kuo Hsia, Jhubei, TW;

Chen-Hua Yu, Hsinchu, TW;

Jui Lin Chao, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/132 (2006.01); G02B 6/12 (2006.01); G02B 6/136 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
G02B 6/132 (2013.01); G02B 6/12004 (2013.01); G02B 6/136 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 25/167 (2013.01); G02B 2006/12104 (2013.01);
Abstract

A method includes patterning a top silicon layer in a substrate to form a plurality of photonic devices. The substrate includes the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer. The method further includes forming a second dielectric layer to embed the plurality of photonic devices therein, forming an interconnect structure over and signally coupling to the plurality of photonic devices, bonding an electronic die to the interconnect structure, thinning the semiconductor layer, and patterning the semiconductor layer that has been thinned to form openings. The openings are filled with a dielectric material to form dielectric regions. Through-vias are formed to penetrate through the dielectric regions to electrically couple to the interconnect structure.


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