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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12628418 B1

PDFFull Text
Date of Patent:
May. 12, 2026

Filed:

Jul. 19, 2023

Semiconductor device with selectively etched dielectric fins

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Zhi-Chang Lin, Hsinchu County, TW;

Wei-Hao Wu, Hsinchu City, TW;

Jia-Ni Yu, New Taipei City, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

HAYNES AND BOONE, LLP

Primary Examiner:

Eric W Jones

Int. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 21/311 (2006.01); H10B 10/00 (2023.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10D 84/853 (2025.01); H01L 21/31111 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 89/10 (2025.01); H10D 64/015 (2025.01); H10D 64/021 (2025.01); H10D 84/0167 (2025.01); H10D 84/0172 (2025.01);
Abstract

A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.

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