The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Jun. 16, 2023
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/853 (2025.01); H10D 84/0172 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract
A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.