The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
May. 25, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Tien-Shun Chang, Hsinchu, TW;
Kuo-Ju Chen, Hsinchu, TW;
Sih-Jie Liu, Hsinchu, TW;
Wei-Fu Wang, Hsinchu, TW;
Yi-Chao Wang, Hsinchu, TW;
Li-Ting Wang, Hsinchu, TW;
Su-Hao Liu, Hsinchu, TW;
Huicheng Chang, Hsinchu, TW;
Yee-Chia Yeo, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/265 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10P 30/20 (2026.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10P 30/20 (2026.01);
Abstract
A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.