The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Feb. 23, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Mickey Hsieh, Hsin-Chu, TW;
Chun-Yang Tsai, Hsinchu, TW;
Kuo-Ching Huang, Hsinchu, TW;
Kuo-Chi Tu, Hsin-Chu, TW;
Pili Huang, Hsin-Chu, TW;
Cheng-Jun Wu, Hsin-Chu, TW;
Chao-Yang Chen, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
The present disclosure relates to a method for forming a ferroelectric memory device. The method includes forming a dielectric layer over a semiconductor substrate and forming a first conductive layer over the dielectric layer. The first conductive layer has a first overall electronegativity. A ferroelectric layer is formed on the first conductive layer. The ferroelectric layer has a second overall electronegativity less than or equal to the first overall electronegativity. A second conductive layer is formed on the ferroelectric layer. The second conductive layer has a third overall electronegativity greater than or equal to the second overall electronegativity. The second conductive layer, the ferroelectric layer, and the first conductive layer are etched to form a polarization switching structure. An ILD layer is formed over the polarization switching structure, and a planarization process is performed on the ILD layer. A first conductive via is formed over the polarization switching structure.