The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

May. 18, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Hong Yu, Clifton Park, NY (US);

David C. Pritchard, Glenville, NY (US);

Navneet K. Jain, Milpitas, CA (US);

James P. Mazza, Saratoga Springs, NY (US);

Romain H. A. Feuillette, Williston, VT (US);

Assignee:

GLOBALFOUNDRIES U.S. Inc, Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2026.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/43 (2025.01); H10D 62/121 (2025.01); H10D 84/0142 (2025.01); H10D 84/83 (2025.01);
Abstract

The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.


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