The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Aug. 23, 2022
Applicant:

Zhuhai Access Semiconductor Co., Ltd., Guangdong, CN;

Inventors:

Xianming Chen, Guangdong, CN;

Lei Feng, Guangdong, CN;

Benxia Huang, Guangdong, CN;

Yejie Hong, Guangdong, CN;

Gao Huang, Guangdong, CN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/4882 (2013.01); H01L 21/565 (2013.01); H01L 23/13 (2013.01); H01L 23/3121 (2013.01); H01L 23/3736 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 24/48 (2013.01); H01L 2224/48229 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/182 (2013.01); H01L 2924/183 (2013.01);
Abstract

A signal-heat separated TMV packaging structure includes an insulating dielectric material, an inner signal line layer arranged in the insulating dielectric material, an outer signal line layer, a heat dissipation metal face and a chip. A first side of the insulating dielectric material is provided with an isolating layer. The outer signal line layer is arranged on a surface of a second side of the insulating dielectric material and is connected with the inner signal line layer through a TMV structure. The heat dissipation metal face is arranged on a surface of the first side of the insulating dielectric material, and is separated from the inner signal line layer. The chip is embedded in the insulating dielectric material, with an active face in electrically-conductive connection with the inner signal line layer and a passive face in heat transfer connection with the heat dissipation metal face.


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