The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Dec. 28, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Alexander Reznicek, Troy, NY (US);

Daniel Schmidt, Niskayuna, NY (US);

Tsung-Sheng Kang, Ballston Lake, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 30/014 (2025.01); H10D 30/024 (2025.01); H10D 30/43 (2025.01); H10D 64/017 (2025.01);
Abstract

A hybrid semiconductor structure, a system, and a method of forming a hybrid semiconductor structure. The hybrid semiconductor structure may include a PFET region, where the PFET region includes a first channel in a fin shape; an NFET region, where the NFET region includes a second channel, the second channel including a nanosheet; and an isolation bar separating the PFET region from the NFET region. The system may include a hybrid semiconductor structure including a PFET region; an NFET region; an isolation bar separating the PFET and NFET region; and a gate surrounding a plurality of sidewalls of the first channel and the second channel. The method may include forming an isolation bar between a first channel material in an NFET region and a second channel material in a PFET region; forming the second channel material into a fin shape; and forming the first channel material into stacked nanosheets.


Find Patent Forward Citations

Xie, Ruilong. (2026). Hybrid cmos with fin and nanosheet architectures (U.S. Patent No. 12622053). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12622053

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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