The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Feb. 03, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jhong-Sheng Wang, Taichung, TW;

Ting-Sheng Huang, Hsinchu, TW;

Jiaw-Ren Shih, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 86/00 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/62 (2025.01); H10D 30/6713 (2025.01); H10D 30/6715 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01); H10D 84/0167 (2025.01); H10D 84/0177 (2025.01); H10D 84/85 (2025.01); H10D 84/853 (2025.01); H10D 86/201 (2025.01); H10D 30/6218 (2025.01); H10D 84/017 (2025.01);
Abstract

A method of manufacturing a semiconductor device includes implanting a channel region of a first transistor and a channel region of a second transistor to have a first conductivity type. The method further includes forming source/drain regions of the first transistor to have the first conductivity type and source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type. The method further includes depositing a first work function layer over the channel region of the first transistor. The method further includes depositing a second work function layer over the channel region of the second transistor, wherein the first work function layer includes a same material as the second work function layer.


Find Patent Forward Citations

Wang, Jhong-Sheng. (2026). Method of making breakdown resistant semiconductor device (U.S. Patent No. 12622044). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12622044

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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