The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2026
Filed:
Dec. 20, 2022
Csmc Technologies Fab2 Co., Ltd., Wuxi, CN;
Southeast University, Nanjing, CN;
Feng Lin, Wuxi, CN;
Chaoqi Xu, Wuxi, CN;
Shuxian Chen, Wuxi, CN;
Chunxu Li, Wuxi, CN;
Li Lu, Nanjing, CN;
Siyang Liu, Nanjing, CN;
Weifeng Sun, Nanjing, CN;
CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi, CN;
SOUTHEAST UNIVERSITY, Nanjing, CN;
Abstract
The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.