The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Jun. 07, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kuiwon Kang, San Diego, CA (US);

Joan Rey Villarba Buot, Escondido, CA (US);

Bohan Yan, San Diego, CA (US);

Manuel Aldrete, Encinitas, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 40/22 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/30 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 40/228 (2026.01); H10W 90/701 (2026.01); H10W 72/07253 (2026.01); H10W 72/07254 (2026.01); H10W 72/07354 (2026.01); H10W 72/07554 (2026.01); H10W 72/234 (2026.01); H10W 72/242 (2026.01); H10W 72/342 (2026.01); H10W 74/15 (2026.01); H10W 90/722 (2026.01); H10W 90/723 (2026.01); H10W 90/752 (2026.01);
Abstract

Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die ('die') to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).


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