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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12610811 B1

PDFFull Text
Date of Patent:
Apr. 21, 2026

Filed:

Jan. 12, 2023

Semiconductor structure, test structure, manufacturing method and test method

Applicant:

Changxin Memory Technologies, Inc., Hefei City, CN;

Inventors:

Deyuan Xiao, Hefei, CN;

Guangsu Shao, Hefei, CN;

Yi Jiang, Hefei, CN;

Xingsong Su, Hefei, CN;

Yunsong Qiu, Hefei, CN;

Assignee:

CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei City, CN;

Attorneys:

SYNCODA LLC

Feng Ma

Primary Examiner:

Alexander G Ghyka

Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/324 (2006.01); H01L 21/56 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/31055 (2013.01); H01L 21/31122 (2013.01); H01L 21/32134 (2013.01); H01L 21/32136 (2013.01); H01L 21/324 (2013.01); H01L 21/56 (2013.01); H01L 21/76816 (2013.01); H01L 21/76819 (2013.01); H01L 21/76831 (2013.01); H01L 21/76837 (2013.01); H01L 21/76883 (2013.01); H01L 21/76885 (2013.01); H01L 22/14 (2013.01); H01L 22/32 (2013.01); H01L 23/3178 (2013.01); H01L 23/53209 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/122 (2025.01);
Abstract

Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

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