The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Jan. 15, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ya-Yi Tsai, Hsinchu, TW;

Sheng-Yi Hsiao, Hsinchu, TW;

Shu-Yuan Ku, Hsinchu, TW;

Ryan Chia-Jen Chen, Hsinchu, TW;

Tzu-Ging Lin, Kaohsiung, TW;

Jih-Jse Lin, Taipei, TW;

Yih-Ann Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/834 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/017 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a fin disposed over a semiconductor substrate, and the fin has a first width. The structure further includes an isolation region disposed around the fin, a gate electrode disposed over the fin and the isolation region, and a fill material disposed in the gate electrode. The fill material is in contact with a top surface of a portion of the semiconductor substrate, the top surface has at least a portion having a substantially flat cross-section, and the portion of the top surface has a second width substantially greater than the first width.


Find Patent Forward Citations

Loading…