The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

May. 28, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chen-Hsuan Tsai, Taitung, TW;

Chin-Chuan Chang, Hsinchu County, TW;

Ying-Ching Shih, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/40 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/3128 (2013.01); H01L 23/4006 (2013.01); H01L 23/49816 (2013.01); H01L 23/5385 (2013.01); H01L 24/16 (2013.01); H10D 64/017 (2025.01); H01L 2023/4087 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A package structure including a wiring substrate, semiconductor dies, and a dielectric layer is provided. The wiring substrate includes die bonding regions and guiding patterns (auxiliary patterns, or dummy patterns) distributed between the die bonding regions. The semiconductor dies are disposed on the die bonding regions and electrically connected to the wiring substrate, wherein the guiding patterns are electrically insulated from the semiconductor dies. The dielectric layer is disposed the semiconductor dies and the wiring substrate, wherein the dielectric layer covers and is in contact with the guiding patterns.


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