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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12599050 B1

PDFFull Text
Date of Patent:
Apr. 07, 2026

Filed:

Jun. 23, 2021

Multi-level die coupled with a substrate

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Omkar Karhade, Chandler, AZ (US);

Sai Vadlamani, Gilbert, AZ (US);

Xavier F. Brun, Chandler, AZ (US);

Hemanth Dhavaleswarapu, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt P.C.

Primary Examiner:

Elias Ullah

Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H10F 77/00 (2025.01); H10H 20/857 (2025.01); H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/50 (2013.01); H01L 23/528 (2013.01); H01L 24/14 (2013.01); H10F 77/00 (2025.01); H10H 20/857 (2025.01); H01L 2021/60022 (2013.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.

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