The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Nov. 28, 2022
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Shang-Yu Chang Chien, Hsinchu County, TW;

Nan-Chun Lin, Hsinchu County, TW;

Hung-Hsin Hsu, Hsinchu County, TW;

Assignee:

POWERTECH TECHNOLOGY INC., Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 74/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/093 (2026.01); H10W 70/611 (2026.01); H10W 74/012 (2026.01); H10W 74/014 (2026.01); H10W 74/016 (2026.01); H10W 74/019 (2026.01); H10W 74/121 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 72/0198 (2026.01); H10W 74/00 (2026.01); H10W 74/142 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, a redistribution layer, at least one bridge chip, at least two active chips, an encapsulant, and an underfill layer. The conductive pillars are disposed on the substrate side by side, the redistribution layer is disposed on the conductive pillars, and the bridge chip is disposed between the substrate and the redistribution layer. The active chips are disposed on the redistribution layer, the bridge chip is coupled between the active chips, and the encapsulant is disposed on the redistribution layer and surrounds the active chips. The underfill layer is disposed between adjacent two of the conductive pillars and between one of the conductive pillars and the bridge chip.


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