The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Apr. 12, 2023
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Shou-Zen Chang, Hsinchu City, TW;

Ming-Han Liao, Hsinchu City, TW;

Min-Cheng Chen, Hsinchu County, TW;

Shang-Shiun Chuang, Taipei City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H04N 25/771 (2023.01); H04N 25/78 (2023.01); H10F 39/18 (2025.01);
U.S. Cl.
CPC ...
H10F 39/802 (2025.01); H04N 25/771 (2023.01); H04N 25/78 (2023.01); H10F 39/182 (2025.01); H10F 39/8053 (2025.01); H10F 39/8063 (2025.01); H10F 39/811 (2025.01);
Abstract

A CMOS image sensor with 3D monolithic OSFET and FEMIM capacitor, including a substrate with CMOS devices formed thereon, a BEOL interconnect layer on the substrate and with BEOL interconnects formed therein, a pixel circuit layer on the BEOL interconnect layer. The OSFETs and FEMIM capacitors are formed in the pixel circuit layer, and a photoelectric conversion layer on the pixel circuit layer and with photodiodes are formed therein, wherein the CMOS devices, the OSFETs, FEMIM capacitors and photodiodes are electrically connected with each other through the BEOL interconnects.


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