The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Jul. 28, 2022
Applicant:

Avago Technologies International Sales Pte. Limited, Singapore, SG;

Inventors:

Sam Karikalan, Ladera Ranch, CA (US);

Sam Zhao, Irvine, CA (US);

Mayank Mayukh, Fort Collins, CO (US);

Liming Tsau, Irvine, CA (US);

Dharmendra Saraswat, Foothill Ranch, CA (US);

Arun Ramakrishnan, Lake Forest, CA (US);

Reza Sharifi, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/49816 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 25/50 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/32145 (2013.01);
Abstract

Tools and techniques for a semiconductor package providing side wall interconnections are provided. An apparatus includes two or more die layers that are bonded together, the first 3D stacked die package comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes two or more side wall pads, wherein each side wall pad of the two or more side wall pads is coupled to an interconnect of a respective die layer of the two or more die layers.


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