The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

May. 08, 2024
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Yu-Hsuan Chang, New Taipei City, TW;

Ching-Wei Li, Hsinchu City, TW;

Jih-San Lee, Hsinchu City, TW;

Tien-Hao Tang, Hsinchu City, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 7/20 (2006.01); H02H 9/04 (2006.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01); H10D 84/80 (2025.01); H10D 89/60 (2025.01);
U.S. Cl.
CPC ...
H10D 89/60 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01); H10D 84/811 (2025.01);
Abstract

An ESD protection circuit using GaN devices, with an ESD protection block including a first sub-block and a second sub-block. The first sub-block includes a trigger coupled to a gate of a power HEMT, a 2DEG resistor coupled to another terminal of the trigger, a LV-HEMT with a gate coupled to another terminal of the trigger and one terminal of the 2DEG resistor and with a source coupled to the gate of the power HEMT and the terminal of the trigger, and a lateral FER coupled to the gate of the LV-HEMT, the another terminal of the trigger and one terminal of the 2DEG resistor, wherein the second sub-block is provided with a device configuration completely symmetrical to the first sub-block, and corresponding devices of the two sub-blocks are coupled with each other.


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