The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Mar. 31, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Shih-Cheng Chen, New Taipei City, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Zhi-Chang Lin, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6739 (2025.01); H01L 21/02603 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/021 (2025.01); H10D 62/121 (2025.01); H10D 64/018 (2025.01); H10D 64/671 (2025.01);
Abstract

A semiconductor device includes a substrate, a first source/drain feature and a second source/drain feature over the substrate, a first semiconductor layer and a second semiconductor layer between the first and the second source/drain features, and a gate between the first and the second source/drain features. A portion of the gate is further between the first and the second semiconductor layers. Moreover, the semiconductor device includes a first inner spacer and a second inner spacer. The first inner spacer is between the first and the second semiconductor layers and further between the portion of the gate and a portion of the first source/drain feature. Furthermore, the portion of the first source/drain feature is between the first semiconductor layer and the second semiconductor layer. The first inner spacer has a U-shaped profile. Additionally, the second inner spacer is between the first inner spacer and the portion of the first source/drain feature.


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