The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2026
Filed:
Jun. 29, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Kam-Tou Sio, Hsinchu, TW;
Cheng-Chi Chuang, Hsinchu, TW;
Chih-Ming Lai, Hsinchu, TW;
Jiann-Tyng Tzeng, Hsinchu, TW;
Wei-Cheng Lin, Hsinchu, TW;
Lipen Yuan, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); G06F 30/394 (2020.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5221 (2013.01); G06F 30/394 (2020.01); H01L 21/76805 (2013.01); H01L 21/76837 (2013.01); H01L 21/76877 (2013.01); H01L 23/5286 (2013.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract
A method of manufacturing an integrated circuit (IC) structure includes forming an opening in a first dielectric material between a first gate structure and a second gate structure by removing a portion of the first dielectric material overlying a fin structure; filling at least part of the opening with a second dielectric material; and forming a contact overlying the fin structure and the second dielectric material.