The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Aug. 30, 2023
Applicant:

Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;

Inventors:

Jiaqi Hong, Shanghai, CN;

Jun Tan, Shanghai, CN;

Qiang Yan, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/76264 (2013.01); H10D 30/031 (2025.01); H10D 30/6748 (2025.01); H10D 30/791 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01);
Abstract

The present application discloses a method for manufacturing a source/drain epitaxial layer of an FDSOI MOSFET, comprising: step, forming a shallow trench isolation on an FDSOI substrate; step, opening a formation region of a source/drain region of the MOSFET; step, performing first epitaxial growth to form a first pure silicon epitaxial layer; step, performing a first etching process to remove polysilicon particles generated from step; and step, performing epitaxial growth to sequentially form a second source/drain epitaxial seed layer, a third source/drain epitaxial bulk layer, and a fourth source/drain epitaxial cap layer on a surface of the first pure silicon epitaxial layer, so the four epitaxial layers are stacked to form the source/drain epitaxial layer.


Find Patent Forward Citations

Loading…