The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Apr. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Cheng-Wei Chang, Taipei City, TW;

Shahaji B. More, Hsinchu City, TW;

Yi-Ying Liu, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01);
Abstract

A method of manufacturing a semiconductor device includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first and second semiconductor layers into a fin structure, forming a dielectric layer across the fin structure, and removing the first semiconductor layers of the fin structure thereby forming gaps between the second semiconductor layers of the fin structure. The method also includes depositing a first metal layer to wrap around the second semiconductor layers thereby forming voids between opposing sidewalls of the dielectric layer, recessing the first metal layer, forming a blocking layer over the recessed first metal layer thereby covering the voids, and depositing a second metal layer over the blocking layer.


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