The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jan. 26, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Christopher J. Penny, Saratoga Springs, NY (US);

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Albert Chu, Nashua, NH (US);

Ruilong Xie, Niskayuna, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Daniel James Dechene, Albany, NY (US);

Eric Miller, Watervliet, NY (US);

Prasad Bhosale, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01);
Abstract

Interconnect structures including signal lines, power lines and ground lines are configured for improvements in routing and scaling. Vertical stacking of the relatively wide power and ground lines allows for additional signal tracks in the same footprint of a standard cell or other electronic device. Alternatively, vertical stacking of the signal lines allows an increased number of signal tracks. Such interconnect structures are formed during back-end-of-line processing using subtractive or damascene interconnect integration techniques.


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