The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jan. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Chieh Lu, Taipei City, TW;

Chih-Yu Chang, New Taipei City, TW;

Yu-Chuan Shih, Hsinchu City, TW;

Huai-Ying Huang, Jhonghe City, TW;

Yu-Ming Lin, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); G11C 5/06 (2006.01); H01L 21/02 (2006.01); H10B 51/30 (2023.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); G11C 5/063 (2013.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01); H01L 21/0228 (2013.01); H10D 62/118 (2025.01);
Abstract

An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.


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