The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Apr. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Hai Li, Portland, OR (US);

Ian Alexander Young, Olympia, WA (US);

Dmitri Evgenievich Nikonov, Beaverton, OR (US);

Julien Sebot, Portland, OR (US);

Raseong Kim, Portland, OR (US);

Chia-Ching Lin, Portland, OR (US);

Punyashloka Debashis, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
H10D 30/701 (2025.01); H10N 50/85 (2023.02);
Abstract

Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.


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