The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Mar. 23, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Tsung-Sheng Kang, Ballston Lake, NY (US);

Daniel Schmidt, Niskayuna, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Alexander Reznicek, Troy, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/518 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor structure includes a gate cut isolation region composed of a top portion and a bottom portion. The top portion of the gate cut isolation region being at a first taper angle and the second portion being at a second taper angle different from the first taper angle. A change from the first taper angle to the second taper angle occurs at an intersection between the top portion of the gate cut isolation region and the bottom portion of the gate cut isolation region. The semiconductor structure further includes a plurality of semiconductor channel layers adjacent to the gate cut isolation region, the plurality of semiconductor channel layers being surrounded by a metal gate stack. A top surface of an uppermost semiconductor channel layer being coplanar with the intersection between the top portion and the bottom portion of the gate cut isolation region.


Find Patent Forward Citations

Loading…