The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Apr. 28, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Yuan Chen, HsinChu, TW;

Lo-Heng Chang, Hsinchu, TW;

Huan-Chieh Su, Changhua County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Szu-Chien Wu, Baoshan Township, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 84/013 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.


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