Selective backside recessing of source and drain regions

Abstract

Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.