The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2026
Filed:
Mar. 28, 2024
Kepler Computing Inc., San Francisco, CA (US);
Biswajeet Guha, Hillsboro, OR (US);
Mauricio Manfrini, Heverlee, BE;
Noriyuki Sato, Palo Alto, CA (US);
James David Clarkson, El Sobrante, CA (US);
Abel Fernandez, Berkeley, CA (US);
Somilkumar J. Rathi, San Jose, CA (US);
Niloy Mukherjee, San Ramon, CA (US);
Tanay Gosavi, Portland, OR (US);
Amrita Mathuriya, Portland, OR (US);
Rajeev Kumar Dokania, Beaverton, OR (US);
Sasikanth Manipatruni, Portland, OR (US);
Kepler Computing Inc., San Francisco, CA (US);
Abstract
A method of fabricating a device includes forming a multi-layer stack comprising a plurality of electrode layers and a first dielectric layer comprising a non-linear polar material. The method further comprises forming a second dielectric layer on the multi-layer stack, annealing the multi-layer stack, and forming a transistor above a second substrate. A third dielectric layer is formed above the transistor. The second dielectric layer can be bonded with the third dielectric layer and the multi-layer stack can be etched to form a capacitor and a plate electrode connected with the capacitor. An electrode structure can be formed, where at least a portion of the electrode structure extends through the plate electrode and couples with a terminal of the transistor.