The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Feb. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsu Ming Hsiao, Hsinchu, TW;

Hsiu-Hao Tsao, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/014 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01);
Abstract

A semiconductor device, along with methods of forming such, are described. The device includes a semiconductor material disposed over a substrate, a first epitaxial source/drain region in contact with a first end of the semiconductor material, a second epitaxial source/drain region in contact with a second end opposite the first end of the semiconductor material, a first dummy gate dielectric layer in contact with the semiconductor material and the first epitaxial source/drain region, a second dummy gate dielectric layer in contact with the semiconductor material and the second epitaxial source/drain region, and an interfacial dielectric disposed between the first and second dummy gate dielectric layers.


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