The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Mar. 25, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chu-An Lee, Hsinchu, TW;

Chen-Hao Wu, Hsinchu, TW;

Peng-Chung Jangjian, Hsinchu, TW;

Chun-Wen Hsiao, Hsinchu, TW;

Teng-Chun Tsai, Hsinchu, TW;

Huang-Lin Chao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/76224 (2013.01); H10D 62/115 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01); H01L 21/31053 (2013.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes an isolation feature formed over a substrate that includes a first fin and a second fin separated from each other by the isolation feature. The semiconductor device structure also includes an insulating fin structure formed in the isolation feature between the first fin and the second fin. The insulating fin structure includes a first insulating fin base partially formed within the isolation feature and a first insulating capping layer formed over a top surface of the first insulating fin base.


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