The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Mar. 17, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Jin Li, Hsinchu, TW;

Che-Hao Chang, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Yung-Cheng Lu, Hsinchu, TW;

Wen-Kai Lin, Yilan County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6713 (2025.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A semiconductor structure and a method of forming is provided. The semiconductor structure includes nanostructures separated from one another and stacked over a substrate, a gate stack wrapping around the nanostructures, and a dielectric fin structure laterally spaced apart from the nanostructures by the gate stack. The dielectric fin structure include a lining layer and a fill layer nested within the lining layer. The lining layer is made of a carbon-containing dielectric material, and a carbon concentration of the lining layer varies in a direction from the gate stack to the lining layer.


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