The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Aug. 08, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shu-Hui Su, Taipei, TW;

Hsin-Li Cheng, Hsinchu, TW;

Felix Yingkit Tsui, Cupertino, CA (US);

Yu-Chi Chang, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/00 (2025.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/58 (2006.01); H10D 1/68 (2025.01);
U.S. Cl.
CPC ...
H10D 1/042 (2025.01); H01L 21/764 (2013.01); H01L 21/76816 (2013.01); H01L 23/5223 (2013.01); H01L 23/585 (2013.01); H10D 1/696 (2025.01); H10D 1/716 (2025.01);
Abstract

Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure comprises a substrate comprising a first trench, wherein the first trench extends into a front side surface of the substrate, a first trench capacitor comprising a plurality of first capacitor electrode layers and a plurality of first capacitor dielectric layers disposed in alternating manner within the first trench and over the front side surface of the substrate, wherein a first air gap is enclosed by the plurality of first capacitor electrode layers and the plurality of first capacitor dielectric layers within the first trench, an interconnect structure disposed over the first trench capacitor, wherein one or more first capacitor electrode layers of the plurality of first capacitor electrode layers are in electrical connection with a first conductive feature in a dielectric layer of the interconnect structure, and a first seal ring structure disposed in the interconnect structure and encircling an interior portion of the substrate, wherein at least a portion of the first seal ring structure is in contact with the first conductive feature.


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