The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Sep. 23, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Deyuan Xiao, Hefei, CN;

Guangsu Shao, Hefei, CN;

Yunsong Qiu, Hefei, CN;

Yi Jiang, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H10B 12/488 (2023.02); H01L 23/528 (2013.01); H10B 12/05 (2023.02); H10B 12/482 (2023.02);
Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, where the substrate includes first grooves arranged at intervals therein along a second direction and extended along a first direction, and a filling layer in the first groove; patterning the substrate, to form second grooves, where the second groove is located on a top surface of the first groove, forming a protective layer on a surface of the substrate, where the protective layer is different from the filling layer; forming a bit line structure at a bottom of the second groove; forming a first isolation layer, where the first isolation layer is located in the second groove and on a top surface of the bit line structure; partially removing the filling layer, where the retained filling layer is flush with an upper surface of the first isolation layer.


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