The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2026
Filed:
Jun. 07, 2023
Applicant:
Intel Ndtm Us Llc, Santa Clara, CA (US);
Inventors:
Rifat Ferdous, Santa Clara, CA (US);
Sung-Taeg Kang, Palo Alto, CA (US);
Golnaz Karbasian, San Jose, CA (US);
Ali Khakifirooz, Brookline, MA (US);
Rohit S. Shenoy, Fremont, CA (US);
Assignee:
Intel NDTM US LLC, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/32 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01);
Abstract
The gap width in a threshold voltage (Vt) distribution for a 3D NAND Flash cell is improved by performing touchup program on a selected portion of the word lines in a block after all of the word lines in the block have been programmed.
Ferdous, Rifat. (2026). Apparatus and method to improve read window budget in a three dimensional nand memory (U.S. Patent No. 12542187). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12542187
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile