The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
Apr. 12, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chien Chang, Hsinchu, TW;
Min-Hsiu Hung, Tainan, TW;
Yu-Hsiang Liao, Hsinchu, TW;
Yu-Shiuan Wang, Taipei, TW;
Tai Min Chang, Taipei, TW;
Kan-Ju Lin, Kaohsiung, TW;
Chih-Shiun Chou, Hsinchu, TW;
Hung-Yi Huang, Hsin-chu, TW;
Chih-Wei Chang, Hsin-Chu, TW;
Ming-Hsing Tsai, Chu-Pei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.