The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Jul. 15, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kuo-Cheng Chiang, Zhubei, TW;

Zhi-Chang Lin, Zhubei, TW;

Guan-Lin Chen, Baoshan Township, TW;

Ting-Hung Hsu, MiaoLi, TW;

Jiun-Jia Huang, Beigang Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/853 (2025.01); H01L 21/02356 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 30/791 (2025.01); H10D 30/792 (2025.01); H10D 30/797 (2025.01); H10D 62/115 (2025.01); H10D 84/0179 (2025.01); H10D 84/0184 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01);
Abstract

A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.


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