Source/drain epitaxial structures for high voltage transistors

Abstract

The present disclosure describes a method for the formation of n-type and p-type epitaxial source/drain structures with substantially co-planar top surfaces and different depths across input/output (I/O) and non-I/O regions of a substrate. In some embodiments, the method includes forming fin structures and a planar portion on a substrate. The method also includes forming first gate structures on the fin structures and second gate structures on the planar portion. The method also includes etching the fin structures between the first gate structures to form first openings and etching the planar portion between the second gate structures to form second openings. Further, the method includes forming first epitaxial structures in the first openings and second epitaxial structures in the second openings, where top surfaces of the first and second epitaxial structures are substantially co-planar and bottom surfaces of the first and second epitaxial structures are not co-planar.