The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Aug. 30, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Seng Kim Ye, Singapore, SG;

Kelvin Tan Aik Boo, Singapore, SG;

Hong Wan Ng, Singapore, SG;

Chin Hui Chong, Singapore, SG;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01G 2/06 (2006.01); H01G 13/00 (2013.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01G 2/06 (2013.01); H01G 13/00 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48195 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49175 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01);
Abstract

Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.


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