The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Mar. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Leonard P. Guler, Hillsboro, OR (US);

Mauro J. Kobrinsky, Portland, OR (US);

Mohit K. Haran, Hillsboro, OR (US);

Marni Nabors, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Charles H. Wallace, Portland, OR (US);

Allen B. Gardiner, Portland, OR (US);

Sukru Yemenicioglu, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01);
U.S. Cl.
CPC ...
H10D 86/00 (2025.01); H01L 21/76283 (2013.01); H10D 86/01 (2025.01);
Abstract

Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.


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