The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2026
Filed:
Nov. 03, 2023
Micron Technology, Inc., Boise, ID (US);
Akira Goda, Setagaya, JP;
Kishore K. Muchherla, San Jose, CA (US);
Shyam Sunder Raghunathan, Woodlands, SG;
Leo Raimondo, Avezzano, IT;
Jung Sheng Hoei, Newark, CA (US);
Xiangang Luo, Fremont, CA (US);
Ashutosh Malshe, Fremont, CA (US);
Jianmin Huang, San Carlos, CA (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.