The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Dec. 21, 2021
Intel Corporation, Santa Clara, CA (US);
Mohammad Hasan, Aloha, OR (US);
Mohit K. Haran, Hillsboro, OR (US);
Leonard P. Guler, Hillsboro, OR (US);
Pratik Patel, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Makram Abd El Qader, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface co-planar with a top surface of the gate structure.