The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Jun. 30, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

I-Wen Wu, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

Fu-Kai Yang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Chang-Yun Chang, Taipei, TW;

Ching-Feng Fu, Taichung, TW;

Peng Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 23/522 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 23/485 (2013.01); H01L 23/5226 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 62/113 (2025.01); H10D 62/115 (2025.01); H10D 84/0149 (2025.01); H10D 84/0153 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01);
Abstract

A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.


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