The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Mar. 24, 2020
Applicant:

Nepes Co., Ltd., Cheongju-si, KR;

Inventors:

Ju Hyun Nam, Cheongju, KR;

Jun Kyu Lee, Cheongju, KR;

Yong Tae Kwon, Cheongju, KR;

Su Yun Kim, Cheongju, KR;

Dong Hoon Oh, Seoul, KR;

Assignee:

NEPES CO., LTD., Cheongju-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/4857 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 2224/214 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A semiconductor package, as a semiconductor package mounted on a circuit board, includes including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.


Find Patent Forward Citations

Nam, Ju. (2026). Semiconductor package and method for manufacturing same (U.S. Patent No. 12525547). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12525547

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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