The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Jun. 03, 2022
Avago Technologies International Sales Pte. Limited., Singapore, SG;
Mayank Mayukh, Fort Collins, CO (US);
Dharmendra Saraswat, Foothill Ranch, CA (US);
Sam Karikalan, Ladera Ranch, CA (US);
Liming Tsau, Irvine, CA (US);
Sam Zhao, Irvine, CA (US);
Arun Ramakrishnan, Lake Forest, CA (US);
Reza Sharifi, Irvine, CA (US);
Avago Technologies International Sales Pte. Limited, Singapore, SG;
Abstract
Novel tools and techniques are provided for implementing mixed dielectric materials for improving signal integrity of integrated electronics packages or semiconductor packages. In various embodiments, a substrate for a semiconductor device includes: a first layer made of a first material; a second layer made of a second material; and a third layer disposed between the first and second layers, and that is made of a third material different from the first and second materials. In some cases, the first, second, and third layers each contains a plurality of gas-filled regions (e.g., but not limited to, an aerogel core of the third layer and/or polymer resin matrix embedded with hollow silica spheres or aerogel spheres of the first and second layers, or the like). Coaxial ground shields around signal lines in the substrate can be used to improve signal integrity. High dielectric constant lossy lines between signal lines can reduce crosstalk.